We invest heavily to deliver the best products to our customers, and so we’re on the hunt for a top-tier FPGA Digital Designer Engineer Intern. The RTL code you write will contribute to our new generation of satellites and earth stations.

Responsibilities

• Maintain and add new functionality to our FPGA code base, including code to control and test our SDR (software-defined radio) and SDN (software-defined network);

• Design custom IP for new features of both Kepler's satellites and ground stations;

• Add support for new sensors/communication interfaces (such as SPI, I2C, UART);

• Work with high-speed FPGA interfaces (e.g. JESD204b, 10G Ethernet, Aurora).

Requirements

• 2+ years in an Electrical or Computer Engineering degree program, or equivalent;

• Experience with Verilog, SystemVerilog, or VHDL. (You will be working in SystemVerilog).

• Currently enrolled in an undergraduate program at a Canadian post-secondary institution and returning to studies after the internship;

• Available for a full-time, 4–16 month internship beginning January 2027;

• We have a strong preference for candidates who can work from our Toronto office at least 2–3 days per week to support collaboration and team engagement. We recognize that exceptional candidates may require a different arrangement and are open to discussing flexibility where appropriate.

Bonus Points

• Experience with DSP (digital signal processing) algorithms;

• Strong skills with C++ and embedded programming;

• Strong scripting experience (e.g. bash, Python, Tcl, etc.);

• Relevant experience through hobbies or a university design team.