We are looking for a Semi-Senior Functional Verification Engineer to join our growing team. The ideal candidate will have hands-on experience with SystemVerilog and UVM methodology, including the development of functional coverage and SystemVerilog Assertions (SVA), with a solid understanding of digital design verification flows.

Responsibilities:

• Develop and maintain UVM-based testbenches for block-level and system-level verification
• Create, run, and debug directed and constrained-random tests
• Implement functional coverage and analyze results to ensure verification completeness
• Write and integrate SystemVerilog Assertions (SVA) to improve design quality
• Work closely with RTL designers to review specifications and define verification strategies
• Debug simulation issues and provide clear feedback to the design team.

Requirements:

• 2–4 years of experience in functional verification
• Strong knowledge of SystemVerilog and UVM methodology
• Practical experience with functional coverage and SystemVerilog Assertions (SVA)
• Familiarity with coverage-driven verification (functional, code coverage)
• Experience with industry-standard simulators (Cadence Xcelium, Synopsys VCS, or equivalent)
• Good problem-solving and debugging skills
• Intermediate/advanced English (written and spoken)

Nice to have:

• Experience with UVM Register Models (RAL)
• Knowledge of Python or scripting languages for automation
• Background in DSP (Digital Signal Processing) or communication systems
• Exposure to formal verification or low-power verification

We offer the opportunity to work on cutting-edge designs in a collaborative and innovative environment. Professional growth and training opportunities in advanced verification methodologies. A flexible and supportive work culture.

Please contact: gwieflng@emtech.com.ar