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ASIC Verification Engineer, DSP Design



Mountain View, CA, USA
Posted on Tuesday, July 25, 2023
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Role Overview:
As a key DSP Design Verification team member, you will be playing a significant role in verifying highly complex DSP designs targeted for advanced automotive applications. You will closely work with verification leads to define and develop verification environments for block and subsystem verification using constrained random verification techniques and verify the complex DSP designs.

What you'll be doing:

  • Responsible for verifying the DSP design at block and subsystem level verification environments.
  • Define and build test benches, reference models, and scoreboards using SV and UVM methodologies
  • Define and implement comprehensive functional coverage plans
  • Analyze code, functional, and test plan coverages to identify verification gaps and achieve 100% coverage closure
  • Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define the processes, methodology, and automation tools to verify complex DSP and SoCs.
  • Work with the different stakeholders and functional leads to ensure high-quality design delivery on time

What you'll have:

  • 5+ years of experience in the design, verification, and validation of complex IPs, SOCs
  • Hands-on experience in building constrained random verification environments, reference models, scoreboards, and directed self-checking tests using SV and UVM methodologies
  • Experience in verifying DSP design is a plus
  • Solid programming and debugging skills in SystemVerilog, UVM, C/C++, Perl/Python.
  • Strong experience in writing test plans, functional coverage plans, and coverage analysis
  • Proficient in debugging complex IP and SOC designsExcellent verbal and written communication skillsAbility to collaborate deeply with cross-functional leads and management teams
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement

Nice to haves:

  • Developing and integrating C/C++ reference model in the simulation environment
  • Experience in verifying ARM-based SOC using C/C++ and SV/UVM methodology
  • Post-silicon bring-up and validation planning and execution