Senior Physical Design Engineer
Software Engineering, Design
Mountain View, CA, USA
Posted on Friday, July 21, 2023
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Aeva is seeking a Physical Design engineer with strong experience in Synthesis, Static Timing Analysis, and design integrity checks including Lint/CDC/RDC. In this role, you will be responsible for design integrity checks, synthesis, and timing analysis of several modules in Aeva digital ASICs.
What you'll be doing:
- As part of this position, your responsibilities will involve pre-silicon implementation and achieving PPA (Power, Performance, and Area) targets through synthesis and implementation processes that begin with RTL and conclude with delivering a high-quality gate-level netlist.
- You are expected to have hands-on experience with most aspects of physical implementation including Lint, CDC, RDC, Synthesis, and Static Timing Analysis.
- Work closely with designers to run industry-standard design integrity tools on modules and sub-systems. Help identify and fix coding issues to enable smooth implementation.
- Collaborate with designers to run Synthesis on modules and sub-systems, and identify and fix timing and implementation issues.
- Work closely with 3rd party IP vendors on proper SDC generation for the IPs and close timing at the IP level
- Collaborate with implementation engineers and designers in SDC generation and verification using industry-standard tools.
- Be a clear communicator with a proven ability to work across functions inside the company, and with partners across the globe.
What you'll have:
- Extensive experience in synthesis and timing closure of modules in advanced process nodes
- Experience working with high-performance designs, identifying strategies to close aggressive timing targets
- Must have worked with 3rd party mixed-signal IP vendors and resolved timing challenges
- Hands-on experience with Lint, CDC, RDC, Synthesis, and STA. Developed methodologies and flows using industry-standard tools with automation.
- BSEE, MSEE, or Ph.D. with 7+ years of relevant experience in physical implementation of Digital ASICs.
Nice to haves:
- Familiarity with developing automotive grade silicon with AEC-Q100 qualification and ISO 26262
What's in it for you:
- Be part of a fast-paced and dynamic team
- Very competitive compensation and meaningful stock grants
- Exceptional benefits: Medical, Dental, Vision, and more
- Unlimited PTO: We care about results, not punching timecards