We invest in visionary teams with transformative ideas.

Join Canaan's extended family.
222
companies
925
Jobs

Staff Design Verification Engineer

Aeva

Aeva

Design
Bengaluru, Karnataka, India
Posted on Tuesday, November 22, 2022
Role Summary
As a senior member of the DSP Design Verification team, you will be playing a significant role in verifying the DSP design for new breeds of SoC and FPGA for advanced perception applications utilizing 4-D Lidar. You will closely work with verification architects to define and develop verification environments for block, subsystem, and full-chip using constrained random verification techniques and verify complex DSP designs.

What you'll be doing:

  • Responsible for verifying state-of-art DSP design at block, subsystems, and full-chip level verification environments.
  • Define and develop testbenches, constrained random verification environments, reference models, and scoreboards using SystemVerilog and UVM methodologies
  • Built self-checking environment using C/C++ reference models and DPI flow
  • Verify DSP blocks against bit-accurate C/C++ reference models
  • Define and execute verification plan for IP, block, subsystem, and full-chip using SV/UVM methodology
  • Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to enhance the existing processes, methodology, and tools to verify complex DSP and SoCs.
  • Identify and write functional coverage groups to improve test/stimulus quality
  • Through coverage, analysis to identify verification gaps and achieve 100% coverage closure
  • Work with the functional leads and cross-functional teams to ensure high-quality DSP IP delivery on time

What you'll have:

  • 12+ years of experience in the design, verification & validation of complex IPs, SOCs
  • Experience in verifying DSP design in advance
  • 5+ years in architecting and building constrained random verification environments, reference models, scoreboards, and directed self-checking tests using SV/UVM methodologies
  • Solid programming skills in SystemVerilog, UVM, C/C++, Perl/Python.
  • Proficient in debugging complex IP and SOC designs
  • Excellent verbal and written communication skills
  • Ability to collaborate deeply with cross-functional leads and management teams
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new processes and methodology for continuous verification improvement

Nice to have:

  • Experience in developing C/C++ reference models and with Verilog DPI flow
  • Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
  • Post-silicon bring-up and validation planning and execution
  • Experience with test plan building tools like Vmanager.
  • Experience with DFT verification.